1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a CMOS device capable of isolating a N well and a P well in back side of a substrate.
2. Description of the Related Art
A complementary metal oxide semiconductor(CMOS) device has a combination structure of a N-channel MOS(NMOS) transistor and a P-channel MOS(PMOS) transistor. This CMOS device has the advantage of a low power consumption compared with a single device such as a NMOS or a PMOS transistor, since DC voltage between power supply terminals is very low. Therefore, the CMOS device is appropriated for low power, high speed and high integration devices.
When manufacturing the CMOS device, for forming NMOS and PMOS transistors respectively, a N well and a P well are necessarily formed. Furthermore, the N well and the P well are isolated by PN junction.
However, in the above CMOS device, a parasitic thyristor exists due to PNPN junction. Therefore, in case voltage is extremely applied to an input terminal of the CMOS device due to noise of power supply voltage, the parasitic thyristor is turned-on. As a result, current extremely flows in the CMOS device, so that the CMOS device is broken. This occurrence is "latch-up".